Professor Univ. Rochester, NY
August 7, 2018
Power Delivery in Heterogeneous Nanoscale Integrated Systems
The focus of this presentation is on the fundamental challenges in delivering power to high speed, high complexity, heterogeneous integrated circuits. The efficient generation and distribution of multiple on-chip power supply voltages require fundamental changes to the power delivery process to provide increased current in next generation nanoscale heterogeneous integrated circuits.
The delivery of high quality power to the on-chip circuitry with minimum energy loss is a fundamental objective of all modern integrated circuits (ICs). To supply sufficient power on-chip, a higher unregulated DC voltage is usually stepped down and regulated within the power delivery system. Power conversion and regulation resources should be efficiently managed to supply high quality power with minimum energy losses within multiple on-chip power domains. The design complexity of a power delivery system increases with greater requirements on the quality of the power supply, limitations of the passive elements, board and package parasitic impedances, and limited number of I/O pins. Furthermore, to satisfy challenging power efficiency and regulation requirements, hundreds of power regulators should be co-designed with thousands of decoupling capacitors, distributing the power locally to billions of on-chip loads.
Four primary components are required to realize an efficient power delivery system: (a) ultra-small voltage converters to generate power close to the load, (b) accurate models to characterize the individual power components, (c) efficient algorithms to analyze the quality of the power delivered to the load circuits, and (d) a co-design methodology to simultaneously determine the optimal location of the on-chip power supplies and decoupling capacitors.
A hybrid combination of a switching and low-dropout regulator as a point-of-load power supply for next generation heterogeneous systems is described. The area of this circuit is significantly smaller than the area of conventional voltage regulators, while maintaining high current efficiency. The proposed circuit provides an adaptive means for distributing multiple local power supplies across an integrated circuit. Another important challenge in the realization of effective power delivery systems is the analysis of this highly complicated structure where individual voltage fluctuations at millions of nodes need to be efficiently determined. Closed-form expressions for the effective resistance between circuit components will be described. This effective resistance model is utilized in the development of a power grid analysis algorithm to compute the node voltages without requiring any iterations. This algorithm drastically lowers computational complexity since iterative procedures to determine IR drop and L di/dt noise are no longer needed.
With the introduction of ultra-small on-chip voltage regulators, there is a need for novel design methodologies to determine the location of these on-chip power supplies and decoupling capacitors. A codesign methodology is presented to simultaneously determine the optimal location of the power supplies and decoupling capacitors within a high performance power delivery network. The effects of the size, number, and location of the power supplies and decoupling capacitors on the power noise are also discussed.
These circuits, algorithms, and design methods will fundamentally change the manner in which power is delivered on-chip, producing a more efficient methodology for generating, distributing, and managing power to the billions of components within a high performance heterogeneous integrated system.
Dr. Friedman received the B.S. degree from Lafayette College in 1979, and the M.S. and Ph.D. degrees from the University of California, Irvine, in 1981 and 1989, respectively, all in electrical engineering.
From 1979 to 1991, he was with Hughes Aircraft Company, rising to the position of manager of the Signal Processing Design and Test Department, responsible for the design and test of high performance digital and analog integrated circuits. He has been with the Department of Electrical and Computer Engineering at the University of Rochester since 1991, where he is a Distinguished Professor, and the Director of the High Performance VLSI/IC Design and Analysis Laboratory. He is also a Visiting Professor at the Technion – Israel Institute of Technology. His current research and teaching interests are in high performance synchronous digital and mixed-signal microelectronic design and analysis with application to high speed portable processors, low power wireless communications, and power efficient server farms.
He is the author of more than 500 papers and book chapters, 16 patents, and the author or editor of 18 books in the fields of high speed and low power CMOS design techniques, 3-D integration, high speed interconnect, and the theory and application of synchronous clock and power delivery and management. Dr. Friedman is the Editor-in-Chief of the Microelectronics Journal, a Member of the editorial board of the Journal of Low Power Electronics and Journal of Low Power Electronics and Applications, and a Member of the technical program committee of numerous conferences. He previously was the Editor-in-Chief and Chair of the Steering Committee of the IEEE Transactions on Very Large Scale Integration (VLSI) Systems, the Regional Editor of the Journal of Circuits, Systems and Computers, a Member of the editorial board of the Proceedings of the IEEE, IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, IEEE Journal on Emerging and Selected Topics in Circuits and Systems, Analog Integrated Circuits and Signal Processing, and Journal of Signal Processing Systems, a Member of the Circuits and Systems (CAS) Society Board of Governors, Program and Technical chair of several IEEE conferences, and a recipient of the IEEE Circuits and Systems Charles A. Desoer Technical Achievement Award and Mac Van Valkenburg Award, a University of Rochester Graduate Teaching Award, and a College of Engineering Teaching Excellence Award. Dr. Friedman is an inaugural member of the University of California, Irvine Engineering Hall of Fame, a Senior Fulbright Fellow, and an IEEE Fellow.