Dr. Yervant Zorian

Chief Architect and Fellow at Synopsys, President of Synopsys Armenia
August 6, 2018

Automotive Electronics Today: Quality, Safety & Security


Given today’s fast growing automotive electronics industry, this keynote will discuss the implications of automotive quality, safety and security requirements on all aspects of the chip lifecycle: design, silicon bring-up, volume production, and particularly in-system test. Today’s automotive safety critical chips need multiple in-system self-test modes, such as power-on self-test and repair, periodic in-field self-test, advanced error correction, etc. This keynote will address these specific in-system approaches and the benefits of selecting ISO 26262 certified solutions to meet functional safety and security requirements, while accelerating time to market for automotive chips.


Dr. Zorian is a Chief Architect and Fellow at Synopsys, as well as President of Synopsys Armenia. Formerly, he was Vice President and Chief Scientist of Virage Logic, Chief Technologist at LogicVision, and a Distinguished Member of Technical Staff AT&T Bell Laboratories. He is currently the President of IEEE Test Technology Technical Council (TTTC), the founder and chair of the IEEE 1500 Standardization Working Group, the Editor-in-Chief Emeritus of the IEEE Design and Test of Computers and an Adjunct Professor at University of British Columbia. He served on the Board of Governors of Computer Society and CEDA, was the Vice President of IEEE Computer Society, and the General Chair of the 50th Design Automation Conference (DAC) and several other symposia and workshops.

Dr. Zorian holds 35 US patents, has authored four books, published over 350 refereed papers and received numerous best paper awards. A Fellow of the IEEE since 1999, Dr. Zorian was the 2005 recipient of the prestigious Industrial Pioneer Award for his contribution to BIST, and the 2006 recipient of the IEEE Hans Karlsson Award for diplomacy. He received the IEEE Distinguished Services Award for leading the TTTC, the IEEE Meritorious Award for outstanding contributions to EDA, and in 2014, the Republic of Armenia’s National Medal of Science.

He received an MS degree in Computer Engineering from University of Southern California, a PhD in Electrical Engineering from McGill University, and an MBA from Wharton School of Business, University of Pennsylvania.


Dr. Eby G. Friedman

Professor Univ. Rochester, NY
August 7, 2018

Power Delivery in Heterogeneous Nanoscale Integrated Systems


The focus of this presentation is on the fundamental challenges in delivering power to high speed, high complexity, heterogeneous integrated circuits. The efficient generation and distribution of multiple on-chip power supply voltages require fundamental changes to the power delivery process to provide increased current in next generation nanoscale heterogeneous integrated circuits.

The delivery of high quality power to the on-chip circuitry with minimum energy loss is a fundamental objective of all modern integrated circuits (ICs). To supply sufficient power on-chip, a higher unregulated DC voltage is usually stepped down and regulated within the power delivery system. Power conversion and regulation resources should be efficiently managed to supply high quality power with minimum energy losses within multiple on-chip power domains. The design complexity of a power delivery system increases with greater requirements on the quality of the power supply, limitations of the passive elements, board and package parasitic impedances, and limited number of I/O pins. Furthermore, to satisfy challenging power efficiency and regulation requirements, hundreds of power regulators should be co-designed with thousands of decoupling capacitors, distributing the power locally to billions of on-chip loads.

Four primary components are required to realize an efficient power delivery system: (a) ultra-small voltage converters to generate power close to the load, (b) accurate models to characterize the individual power components, (c) efficient algorithms to analyze the quality of the power delivered to the load circuits, and (d) a co-design methodology to simultaneously determine the optimal location of the on-chip power supplies and decoupling capacitors.

A hybrid combination of a switching and low-dropout regulator as a point-of-load power supply for next generation heterogeneous systems is described. The area of this circuit is significantly smaller than the area of conventional voltage regulators, while maintaining high current efficiency. The proposed circuit provides an adaptive means for distributing multiple local power supplies across an integrated circuit. Another important challenge in the realization of effective power delivery systems is the analysis of this highly complicated structure where individual voltage fluctuations at millions of nodes need to be efficiently determined. Closed-form expressions for the effective resistance between circuit components will be described. This effective resistance model is utilized in the development of a power grid analysis algorithm to compute the node voltages without requiring any iterations. This algorithm drastically lowers computational complexity since iterative procedures to determine IR drop and L di/dt noise are no longer needed.

With the introduction of ultra-small on-chip voltage regulators, there is a need for novel design methodologies to determine the location of these on-chip power supplies and decoupling capacitors. A codesign methodology is presented to simultaneously determine the optimal location of the power supplies and decoupling capacitors within a high performance power delivery network. The effects of the size, number, and location of the power supplies and decoupling capacitors on the power noise are also discussed.

These circuits, algorithms, and design methods will fundamentally change the manner in which power is delivered on-chip, producing a more efficient methodology for generating, distributing, and managing power to the billions of components within a high performance heterogeneous integrated system.


Dr. Friedman received the B.S. degree from Lafayette College in 1979, and the M.S. and Ph.D. degrees from the University of California, Irvine, in 1981 and 1989, respectively, all in electrical engineering.

From 1979 to 1991, he was with Hughes Aircraft Company, rising to the position of manager of the Signal Processing Design and Test Department, responsible for the design and test of high performance digital and analog integrated circuits. He has been with the Department of Electrical and Computer Engineering at the University of Rochester since 1991, where he is a Distinguished Professor, and the Director of the High Performance VLSI/IC Design and Analysis Laboratory. He is also a Visiting Professor at the Technion – Israel Institute of Technology. His current research and teaching interests are in high performance synchronous digital and mixed-signal microelectronic design and analysis with application to high speed portable processors, low power wireless communications, and power efficient server farms.

He is the author of more than 500 papers and book chapters, 16 patents, and the author or editor of 18 books in the fields of high speed and low power CMOS design techniques, 3-D integration, high speed interconnect, and the theory and application of synchronous clock and power delivery and management. Dr. Friedman is the Editor-in-Chief of the Microelectronics Journal, a Member of the editorial board of the Journal of Low Power Electronics and Journal of Low Power Electronics and Applications, and a Member of the technical program committee of numerous conferences. He previously was the Editor-in-Chief and Chair of the Steering Committee of the IEEE Transactions on Very Large Scale Integration (VLSI) Systems, the Regional Editor of the Journal of Circuits, Systems and Computers, a Member of the editorial board of the Proceedings of the IEEE, IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, IEEE Journal on Emerging and Selected Topics in Circuits and Systems, Analog Integrated Circuits and Signal Processing, and Journal of Signal Processing Systems, a Member of the Circuits and Systems (CAS) Society Board of Governors, Program and Technical chair of several IEEE conferences, and a recipient of the IEEE Circuits and Systems Charles A. Desoer Technical Achievement Award and Mac Van Valkenburg Award, a University of Rochester Graduate Teaching Award, and a College of Engineering Teaching Excellence Award. Dr. Friedman is an inaugural member of the University of California, Irvine Engineering Hall of Fame, a Senior Fulbright Fellow, and an IEEE Fellow.

Sebastian Fischmeister profile

Dr. Sebastian Fischmeister

Associate Professor, Univ. Waterloo, On
August 8, 2018

Challenges in System Safety and Security of Future Automotive Platforms


For decades, safety was the dominating topic for cyberphysical systems. Safety of a system ensures that in the case of faults, the system is still highly unlikely to cause harm to users, capital infrastructure, or the environment. With the advent of connectivity, security is now becoming an equally important topic as connectivity enables scalable attacks. Unfortunately the complexity of today’s systems prevents engineers from gaining a deep understanding of systems, and consequently, new approaches for safety and security are necessary. 

This talk presents these challenges in the context of automotive systems. The talk discusses automation and autonomy of automotive systems, safety vs. security for connected vehicles, and in general shows the need for merging safety and security research for further advances in electronics, software, and systems for next-generation automated/autonomous systems.


Sebastian Fischmeister is an Associate Professor at the University of Waterloo, leads the Real-time Embedded Software Group, and is appointed as Executive Director at the Waterloo Centre for Automotive Research.

Sebastian Fischmeister performs systems research at the intersection of software technology, distributed systems, and formal methods. His preferred application area is safety-critical embedded real-time systems. Key highlights of his research include a framework for Real-time Ethernet, dynamic binary instrumentation for time-aware systems, and real-time capable runtime monitoring. A variant of his real-time communication framework was used to promote the ASTM F29.21 standard on the Integrated Clinical Environment. Jointly with industry and researchers, he built the APMA Connected Vehicle Technology Demonstrator as well as several CES demos including the Renesas 2017 and 2017 Autonomous Vehicle as well as the DENSO 2018 Driving AI demonstrator. He is now working on data-driven analysis for assessing the safety and security of mission-critical systems. Sebastian is a licensed Canadian Professional Engineer, and active in international standardization through committee memberships in the Standards Council of Canada, the International Electrotechnical Commission, and the Institute of Electrical and Electronics Engineers.