Tutorial 2


Neuromorphic Computing: Algorithms, Devices, and Circuits

Vishal Saxena, University of Idaho


In 2015, U. S. Office of Science and Technology (OSTP) announced a grand challenge which is supported by federal agencies and the IEEE: “Create a new type of computer that can proactively interpret and learn from data, solve unfamiliar problems using what it has learned, and operate with the energy efficiency of the human brain.” In alignment with this, large-scale integration of CMOS mixed signal integrated circuits and nanoscale emerging devices, such as the phase-change (PCRAM) and resistive RAM (RRAM), can enable a new generation of Neuromorphic computers that can be applied to a wide range of machine learning problems. This tutorial combines an overview of recent advances in energy-efficient Neuromorphic Computing circuits and systems for embedded deep learning applications. The tutorial aims to provide a complete picture to the audience; starting from system level architecture to the transistor- and device-level design trade-offs. Case studies will be presented for Neuromorphic System-on-a-chip (NeuSoC) with applications to spike-based machine learning followed by recent advances in the area spiking neural networks and neuromorphic hardware.


Dr. Vishal Saxena is an Associate Professor in the department of Electrical and Computer Engineering at the University of Idaho. His research is in the area of Analog, Mixed-signal, RF/mmWave, and Photonic integrated circuit (IC) and system design.

Dr. Saxena received the B. Tech. in Electrical Engineering from the Indian Institute of Technology Madras, India in 2002, and the M.S. and Ph.D. degrees in Electrical and Computer Engineering from Boise State University, Boise, ID, in 2007 and 2010 respectively. In 2010, he joined the electrical and Computer engineering Department, Boise State University, Boise, ID, USA. Since Fall 2016 he is an Associate Professor and Micron Endowed Chair the the ECE department at the University of Idaho. Previously, he was a Senior Design Engineer with Midas Communications (a startup out of IIT Madras) from 2002-2004, and has worked as Analog design intern for Micron (Boise, ID), and Cisco-Lightwire (Allentown, PA). His research interests include high-speed data converters, CMOS photonic interconnects, clock & data recovery circuits, RF/mmWave photonic circuits, post-CMOS electronics, and Neuromorphic integrated circuits.
Dr. Saxena is a member of IEEE, Eta kappa Nu and Tau Beta Phi. He is a recipient of 2015 National Science Foundation CAREER Award, and 2016 Air Force Office of Sponsored Research (AFOSR) Young Investigator (YIP) award. He has served as an Associate Editor for the IEEE Transactions on Circuits and Systems-II: Express Briefs. Currently, he is serving on the steering committee for the IEEE Midwest Symposium on Circuits and Systems, and is active in the Boise section of the IEEE Solid-State Circuits Society (SSCS) chapter as its inaugural Chair.